Semiconductor integrated circuits are manufactured by forming an array of separate dies on a common semiconductor wafer. Upon completion of processing steps forming the circuitry on the wafer, the wafer is scored and diced to form individual chips which are mounted in individual packages.
During processing, the wafer is treated to form specified regions of insulating, conductive, and semiconductor type materials. For example, conductive regions of polysilicon are conventionally formed in trenches of a silicon substrate to constitute bonding pads, high density interconnections, capacitor plates, etc. of static random access memories (SRAM), microprocessors, and other integrated circuits.
FIGS. 1A and 1B depict an initial processing stage for forming an integrated circuit. A silicon wafer constitutes silicon substrate 20 with a trench 22 formed therein. A high temperature polysilicon layer 24 is formed approximately 1.6 microns thick on the exposed surface of the substrate and in trench 22. Residual polysilicon bordering trench 22 must be removed to leave polysilicon only in the trench. Removal of the residual polysilicon can be performed by plasma etching which nominally removes polysilicon at a rate of approximately 4,000.ANG. to 6,000.ANG. a minute. Alternatively, residual polysilicon can be removed by chemical mechanical planarization or polishing (CMP) to remove polysilicon at a rate of approximately one micron per minute. This latter process is simpler, faster and less expensive to perform.
A polisher for performing CMP is schematically depicted is FIG. 2. Such apparatus are further described in U.S. Pat. Nos. 4,193,226 and 4,811,522 to Gill, Jr. and U.S. Pat. No. 3,841,031 to Walsch, the disclosures thereof being incorporated herein by reference. A commercially available wafer polisher is the Model 372 Polisher manufactured by Westech Systems, Inc.
Referring to FIG. 2, polisher 100 includes a twenty-four inch diameter rotatable aluminum polishing platen 102. Polish pad 104 is a RODELL Suba IV perforated polyester nap mounted on platen 102. Platen 102 and polish pad 104 are driven by a microprocessor controlled motor (not shown) to spin at approximately 100 RPM and to maintain a nominal temperature of 41 degrees Celsius. Wafer 106 has a diameter of between five to seven inches and is mounted on the bottom of a rotatable polishing head 108 so that a lower major surface of wafer 106 to be polished is positionable to contact underlying polish pad 104.
Wafer 106 and polishing head 108 are attached to a vertical polish spindle 110 which, in turn, is rotatably mounted in a lateral robotic arm 112. Robotic arm 112 rotates the polishing head 108 at approximately 25 revolutions per minute in the same direction as platen 102 and radially positions the polishing head over a range of 20 to 30 millimeters at a speed of 3 millimeters per second. The arm also vertically positions head 108 to bring wafer 106 into contact with polish pad 104 and maintain a polishing contact pressure of 6 pounds per square inch, or 192 pounds of down force, for a typical six to seven inch diameter wafer.
A slurry tube 114 opposite polishing head 108 above polish pad 104 dispenses and evenly saturates the pad with slurry 116. The slurry is a potassium hydroxide base solution having a pH of approximately 10.5 to 11.0, such as Nalco 2371. Using this slurry, it is possible to polish through the 1.6 micron thick polysilicon layer 24 in approximately 2.5 minutes.
The resultant polysilicon pad 26 after removal of residual polysilicon by CMP is shown in FIG. 3. If polysilicon pad 26 has an area on the order of 50 microns square and 5,000.ANG. DGEP, the pad will be dished out during polishing with more polysilicon being removed in a central portion than at peripheral portions of the pad. The amount of polysilicon loss can be as much as the total thickness of the trench at the center area. This is due to compliance of polish pad 104. Heat generated by polish pad 104 during polishing increases an exothermic reaction between the slurry and polysilicon. Thus, a central portion of the relatively soft polysilicon is more rapidly removed than peripheral portions when soft polishing pad 104 conforms under pressure to the polysilicon surface.
To minimize dishing of the polysilicon during planarization, the polysilicon may be formed in a plurality of elongate trenches with intervening ridges of harder silicon oxide substrate material. The silicon oxide is more resistant to polishing than the relatively softer polysilicon and therefore acts as a polishing stop. The ratio of polysilicon to intervening silicon oxide surface area is adjustable based on the acceptable degree of dishing and the total area of polysilicon required. Typically, a polysilicon-to-silicon dioxide ratio in the range of one to one is satisfactory.
Referring to FIG. 4, a method of forming a polysilicon region in a substrate 20 using substrate silicon dioxide as a polishing stop includes a step of forming a plurality of parallel trenches 28 with intervening silicon oxide ridges 34. The trenches can be formed by conventional techniques including photo and ion etching. A polysilicon film 30 (FIGS. 5A and 5B) is formed on the exposed surface of substrate 20 including ridges 34 and trenches 28. The wafer is then polished using CMP as described above to remove residual polysilicon.
Because the intervening silicon oxide ridges are resistant to CMP, polishing is inhibited upon removal of the residual polysilicon when encountering the relatively harder silicon oxide ridges 34 that act as a polishing stop. The resultant structure, shown in FIGS. 6A and 6B, includes a plurality of elongate polysilicon filled trenches 32 having upper surfaces coplanar with intermediate silicon oxide ridges 34 and peripheral portions of substrate 20.
After CMP, connective structures, such as silicide/aluminum interconnect layer 36 (FIG. 7), can be formed on polysilicon filled trenches 32. Subsequent processing steps are performed using conventional methods which may include subsequent CMP of overlying layers.
A problem with CMP is the need to determine the required degree of polishing to avoid underpolishing and overpolishing. Referring to FIG. 8, if polishing is incomplete, residual polysilicon bridges 38 remain on silicon oxide ridges 36 and on peripheral surfaces 40 of substrate 20. The residual polysilicon bridges are conductive and tend to short-circuit polysilicon filled trenches 32 to surrounding structures. Conversely, although the intermediate silicon oxide ridges 34 impede overpolishing, some dishing of the array of polysilicon filled trenches 32 occurs as shown in FIG. 9. This is due to mechanical erosion, i.e., scraping away, of the silicon oxide due in part to polishing pad compliance.
Conventionally, polishing is performed for a time period predetermined to completely remove residual portions of the polysilicon without overpolishing and resultant dishing. The time is determined based on previous trial runs and taking into consideration polishing conditions including substrate and slurry properties, surface area, etc. However, this open loop technique is error prone and does not account for processing variations nor is it readily adaptable to different products without extensive trialing runs.
Prior art solutions to overpolishing include monitoring wafer induced drag of the polishing platen and detecting a change in a sense current through the wafer.
U.S. Pat. Nos. 5,036,015 and 5,069,002 of Sandhu et al. describe a method and apparatus for detecting a planar endpoint during CMP of a wafer. The planar endpoint is detected by sensing a change in friction between the wafer and a polishing surface caused by removal of the oxide coating of the wafer and polish pad contact of a hard lower layer. Resistance is detected by measuring current changes of electric motors rotating the wafer and/or the polishing platen.
U.S. Pat. No. 4,793,895 of Kaanta et al. describes an apparatus and method for monitoring the conductivity of a semiconductor wafer during polishing. A polishing pad includes embedded active and passive electrodes therein. A detector connected to the electrodes monitors a current between them as the wafer is lapped by the polishing pad. An etch endpoint of the wafer is determined by the magnitude of the detected current.
A disadvantage of the prior art methods and apparatus for detecting a polishing endpoint is the requirement for modification to the drive system of the polisher and/or to the polishing pad. Further, the prior art systems require significant additional circuitry that must be calibrated for particular wafer polishing characteristics and conductivity. There is the additional drawback of possible damage to the wafer by methods requiring electrical probing to determine an endpoint. The more passive drag detecting systems are subject to calibration error as motor characteristics change over time and under varying external loading conditions.
Accordingly, a need exists for an accurate device and method for accurately detecting a CMP endpoint.
A need further exists for a CMP endpoint detector and detection method able to be implemented without extensive modification to existing polishing equipment.
A need further exists for a CMP endpoint detector and detection method that accommodate a variety of manufacturing variables without requiring recalibration.
A need further exists for a CMP endpoint detector and detection method that does not pose a damage hazard to a wafer being polished.